The present invention relates to push-pull amplifier circuits that comprise CMOS transistors and perform class-AB operations. The device of the present invention relates to differential amplifier circuits that are suitable for use in power conservation type devices such as portable telephones, which should secure the prescribed service life for batteries.
Conventionally, push-pull amplifier circuits comprising CMOS transistors have been widely used. FIG. 4 is a circuit diagram of a conventional device. In this figure, an input circuit 1 provides transistors T2 and T5 for constituting a current mirror circuit, a transistor T6 whose gate terminal inputs a positive input signal +IN, and a transistor T3 whose gate terminal inputs a negative input signal xe2x88x92IN. The current mirror circuit is connected with a positive voltage source VDD. A bias circuit 2 comprises a resistor R1 for setting an operation bias point, and a transistor Ti for generating bias voltage, wherein it is inserted between the positive voltage source VDD and reference voltage VSS. A transistor T4 is an element that supplies a bias current to the input circuit 1. A level shift circuit 3 comprises transistors T9 and T10. An output circuit 4 comprises output transistors T7 and T8 as well as an output terminal OUT.
In the device having the aforementioned configuration, the voltage that is calculated by subtracting voltage drop of the transistor T1 from the difference voltage between the positive voltage source VDD and reference voltage VSS is applied to the resistor R1 in the bias circuit 2, so that an electric current is forced to flow into a series circuit in which the resistor R1 and the transistor T1 are connected to an NB node. The magnitude of this current is supplied as the form of bias voltage to each element via the NB node, thus determining an operation point for each element. In the input circuit 1, the transistors T3 and T6 are identical to each other in characteristics, and the transistors T2 and T5 are identical to each other in characteristics. An N3 node is a common connection point between the transistors T5 and T6, so that an N3 node voltage VN3 may greatly vary in response to variations of the difference voltage (V+INxe2x88x92Vxe2x88x92IN) between the positive input signal voltage V+IN and negative input signal voltage Vxe2x88x92IN. That is, the voltage gain is increased by using the negative resistance, which is established by drain currents ID and drain-source voltages VDS of the transistors T5 and T6, as an active load.
The output circuit 4 is an active load in which the output transistor T8 acts as a load for the output transistor T7, wherein a signal is applied through the transistor T9 to the output transistor T8 to operate. The current of the output transistor T7 varies in response to the N3 node voltage VN3. A capacitor Cc is reduced in gain due to high frequencies to avoid oscillation. Variations of this current is converted to a signal having a large amplitude by the active load, so that the signal is output from the output terminal OUT. The level shift circuit 3 converts the difference voltage (V+INxe2x88x92Vxe2x88x92IN), supplied from the input circuit 1, in voltage level and supplies it to the output circuit 4.
In order to perform a class-A operation ensuring linear signal amplification, bias currents are normally forced to flow, regardless of the existence of the input signal. On the other hand, in the case of the high power amplifier circuit that performs a class-B operation, the bias voltage is set to zero so as to avoid the bias current flowing in a non-signal mode. However, the class-B operation may cause the crossover distortion due to the non-linearity of the characteristic in proximity to zero current. Therefore, in order to avoid occurrence of the crossover distortion, a class-AB operation is used to allow a small bias current to flow.
However, the conventional technology has a problem in that characteristic variations may easily occur because the operation point of the output circuit would vary due to manufacture differences and power variations. Therefore, a small bias current is forced to flow in a non-signal mode in order to secure some margins. It is required that portable telephones should secure one-hundred hours or more per a single battery with respect to the reception wait time; hence, the bias current should be extremely reduced in a non-signal mode. The present invention is provided to solve the aforementioned problems. It is an object of the invention to provide a differential amplifier circuit in which the operation point of the output circuit is stable, and which requires an extremely small amount of bias current compared to the maximal output current in a non-signal mode.
A differential amplifier circuit of the present invention solving the aforementioned problems comprises as shown in FIG. 1 an input circuit 10 for producing a difference voltage signal between the positive input signal and negative input signal, a feedback bias circuit 20 that inputs the difference voltage signal supplied from the input circuit 10 to provide a bias voltage corresponding to the difference voltage signal and that performs feedback controls on the bias voltage by feeding back an output current, an output circuit 30 for supplying the load with the output current corresponding to the bias voltage, and a current detection circuit 40 that detects the output current to provide it to the feedback bias circuit 20, wherein class-AB amplification is performed in such a way that the bias voltage has a current value close to zero when the difference voltage signal is substantially zero.
In the device having the aforementioned configuration, class-AB amplification is performed in such a way that when no signal is applied to the input circuit 10, the feedback bias circuit 20 supplies the output circuit with the bias voltage whose current consumed is small compared to the maximal output current. The current detection circuit 40 detects the output current to feed back it to the feedback bias circuit 20, which in turn performs feedback controls on the bias voltage by feeding back the output current. Therefore, even though manufacture differences and power variations exist, it is possible to obtain a differential amplifier circuit in which the operation point of the output circuit is stable.
Preferably, the input circuit 10 comprises a first transistor MP2 whose gate terminal inputs a positive input signal, and a second transistor MP1 whose gate terminal inputs a negative input signal, wherein source terminals of the first and second transistors are connected to a positive voltage source VDD via a constant current source transistor MP3, and their drain terminals are connected to the aforementioned feedback bias circuit. Both the first and second transistors are identical to each other in characteristics; thus, it is possible to produce an accurate difference voltage signal.
Preferably, the output circuit 30 comprises a first output transistor MP17 and a second output transistor MN11 that are connected between the positive voltage source VDD and reference voltage GND, Vss, wherein the bias voltage supplied from the feedback bias circuit 20 is applied to source terminals of the first and second output transistors, and the first and second output transistors are commonly connected to an output terminal. Due to an active load effect of the first and second output transistors, small variations of the bias voltage are converted into a signal having a large amplitude, which is output from the output terminal.
Preferably, the current detection circuit 40 comprises a first current detection transistor MP16 in which the bias voltage applied to the first output transistor MP17 is supplied to the gate terminal, and the voltage of the positive voltage source VDD is supplied to the source terminal, and a second current detection transistor MN10 in which the bias voltage applied to the second output transistor MN11 is supplied to the gate terminal, and the reference voltage GND, VSS is supplied to the source terminal. Thus, it is suitable for realizing the output current of the output circuit 30 being fed back to the feedback bias circuit 20. In addition, it is possible to constitute the current detection circuit 40 comprising a current control transistor MP12 in which the bias current applied to the first output transistor MP17 is supplied to the gate terminal, and the voltage of the positive voltage source VDD is supplied to the source terminal, and a third current detection transistor MN23 in which the bias voltage applied to the second output transistor MN11 is supplied to the gate terminal, and the reference voltage GND, VSS is supplied to the source terminal. Thus, it is possible to simplify the circuit configuration compared to the configuration defined in claim 4.